Algorithm-Level Low-Power Technology for the Channel Decoding Coprocessor of the Network Processor

In this paper, a new low power reed-solomon decoding algorithm (LP-RSA) is proposed, with the scenario that the RS decoder is integrated as a coprocessor of network processor. The proposed LP-RSA could dynamically judge the number of error symbols in advance and then close the unnecessary polynomial operations as soon as possible. By inserting the dynamic error pre-judgment circuit, the implemented coprocessor of RS decoder, which complies with the proposed LP-RSA, could turn the unnecessary processing circuits into sleep status to prevent the unavailable toggling of them and reduce the power of the coprocessor of RS decoder as well as the power of network processor. Under the same testing environment, the proposed LP-RSA allows the RS coprocessor achieving about 66.1% gain in power saving. At the same time, the proposed algorithm will help to extend the application range of network processor in the communication system with low power characteristic.