• 中国精品科技期刊
  • CCF推荐A类中文期刊
  • 计算领域高质量科技期刊T1类
Advanced Search
Li Yang, Ma Ziqiang, Lin Jingqiang, Meng Lingjia, Li Bingyu, Miao Li, Gao Fei. Survey of Transient Execution Attacks[J]. Journal of Computer Research and Development. DOI: 10.7544/issn1000-1239.202440167
Citation: Li Yang, Ma Ziqiang, Lin Jingqiang, Meng Lingjia, Li Bingyu, Miao Li, Gao Fei. Survey of Transient Execution Attacks[J]. Journal of Computer Research and Development. DOI: 10.7544/issn1000-1239.202440167

Survey of Transient Execution Attacks

Funds: This work was supported by the Natural Science Foundation of Ningxia Hui Autonomous Region of China (2021AAC03078), the Key Research and Development Program of Ningxia Hui Autonomous Region (2021BEB04004, 2021BEB04047, 2022BDE03008), and the Graduate Science and Technology Innovation Foundation of Ningxia University (CXXM2023-20).
More Information
  • Author Bio:

    Li Yang: born in 1999. M.S. candidate. Student member of CCF. His main research interests include computer system security and information security

    Ma Ziqiang: born in 1990. PhD, associate professor. Member of CCF. His main research interests include Computer system security, blockchain application security, network traffic identification

    Lin Jingqiang: born in 1978. PhD, professor. Member of CCF. His main research interests include applied cryptography, network security and system security.(linjq@ustc.edu.cn

    Meng Lingjia: born in 1996. PhD candidate. Student member of CCF. His main research interests include system security and applied cryptography.(menglingjia@iie.ac.cn

    Li Bingyu: born in 1990. PhD, associate professor. Member of CCF. His main research interests include cryptographic application security, network security.(libingyu@buaa.edu.cn

    Miao Li: born in 1986. PhD, associate professor. Member of CCF. Her main research interests include cyberspace security, information security.(limiao_smile@nxu.edu.cn

    Gao Fei: born in 1995. M.S candidate. Student member of CCF. Her main research interests include system security and information security.(gaofei@stu.nxu.edu.cn

  • Received Date: March 11, 2024
  • Revised Date: September 18, 2024
  • Accepted Date: October 14, 2024
  • Available Online: October 20, 2024
  • Transient execution attacks (TEAs) exploit processor optimizations to bypass security checks and exfiltrate sensitive information through covert channels. Among them, Meltdown and Spectre attacks have become prominent, affecting mainstream commercial processors such as Intel, ARM, and AMD. Despite the defensive measures implemented by processor manufacturers, variants of these attacks continue to be discovered and disclosed by researchers. To improve the understanding of TEAs and deploy robust defenses, this paper comprehensively analyzes TEAs under various covert channels. Initially, the common characteristics of TEAs are extracted, and a novel model for TEAs is systematically constructed. Subsequently, we summarize the various types of covert channels involved in existing research, classify the TEAs into three types: Meltdown type attacks driven by out-of-order execution (OoOE), Spectre type attacks driven by branch misprediction, and microarchitecture data sampling (MDS) type attacks driven by data misprediction, and delineate the key aspects and relationships of each type of attack. Notably, this paper systematically compiles and categorizes MDS type attacks for the first time. Then, the capabilities of each attack variant were meticulously analyzed and evaluated from three dimensions: covert channel, attack applicable scenarios, and microarchitecture immunity status, which aids security researchers in developing new, more destructive attack types based on the deficiencies of the existing attack-related research. Finally, combined with the above-mentioned comprehensive and in-depth analysis and summary of processor microarchitecture and covert channels, this paper anticipates the future trajectory of TEAs research, hoping to provide strong support for subsequent research work.

  • [1]
    Lipp M, Schwarz M, Gruss D, et al. Meltdown: Reading kernel memory from user space[C]//Proc of the 27th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2018: 18−33
    [2]
    Kocher P, Horn J, Fogh A, et al. Spectre attacks: Exploiting speculative execution[C]//Proc of the 2019 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2019: 1−19
    [3]
    Szefer J. Survey of microarchitectural side and covert channels, attacks, and defenses[J]. Journal of Hardware and Systems Security, 2019, 3(3): 219−234 doi: 10.1007/s41635-018-0046-1
    [4]
    Bhattacharyya A, Sandulescu A, Neugschwandtner M, et al. Smotherspectre: Exploiting speculative execution through port contention[C]//Proc of the 2019 ACM SIGSAC Conf on Computer and Communications Security. New York: ACM, 2019: 785−800
    [5]
    Fustos J, Bechtel M, Yun H. Spectrerewind: Leaking secrets to past instructions[C]//Proc of the 4th ACM Workshop on Attacks and Solutions in Hardware Security. New York: ACM, 2020: 117−126
    [6]
    Qiu Pengfei, Gao Qiang, Liu Chang, et al. Pmu-spill: A new side channel for transient execution attacks[J]. IEEE Transactions on Circuits and Systems I: Regular Papers, 2023, 70(12): 5048−5059 doi: 10.1109/TCSI.2023.3298913
    [7]
    De Meulemeester J, Purnal A, Wouters L, et al. SpectrEM: Exploiting Electromagnetic emanations during transient execution[C]//Proc of the 32nd USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2023: 6293−6310
    [8]
    Yarom Y, Falkner K. Flush+ Reload: A high resolution, low noise, L3 cache side-channel attack[C]//Proc of the 23rd USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2014: 719−732
    [9]
    Ristenpart T, Tromer E, Shacham H, et al. Hey, you, get off of my cloud: Exploring information leakage in third party compute clouds[C]//Proc of the 16th ACM Conf on Computer and Communications Security. New York: ACM, 2009: 199−212
    [10]
    Osvik D A, Shamir A, Tromer E. Cache attacks and countermeasures: The case of AES[C]//Proc of the 2006 The Cryptographers’ Track at the RSA Conf on Topics in Cryptology. Berlin: Springer, 2006: 1−20
    [11]
    Gullasch D, Bangerter E, Krenn S. Cache games bringing access based cache attacks on AES to practice[C]//Proc of the 2011 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2011: 490−505
    [12]
    Briongos S, Malagón P, Moya J M, et al. Reload+ refresh: Abusing cache replacement policies to perform stealthy cache attacks[C]//Proc of the 29th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2020: 1967−1984
    [13]
    Liu Fangfei, Yarom Y, Ge Qian, et al. Last-level cache side-channel attacks are practical[C]//Proc of the 2015 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2015: 605−622
    [14]
    Gruss D, Maurice C, Wagner K, et al. Flush+ Flush: A fast and stealthy cache attack[C]//Proc of the 13th Int Conf on Detection of Intrusions and Malware, and Vulnerability Assessment. Berlin: Springer, 2016: 279−299
    [15]
    Lipp M, Gruss D, Spreitzer R, et al. ARMageddon: Cache attacks on mobile devices[C]//Proc of the 25th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2016: 549−564
    [16]
    Disselkoen C, Kohlbrenner D, Porter L, et al. Prime + abort: A timer-free high-precision l3 cache attack using intel TSX[C]//Proc of the 26th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2017: 51−67
    [17]
    Van Bulck J, Minkin M, Weisse O, et al. Foreshadow: Extracting the keys to the Intel SGX kingdom with transient out-of-order execution[C]//Proc of the 27th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2018: 991−1008
    [18]
    Mukhtar M A, Bhatti M K, Gogniat G. Architectures for security: A comparative analysis of hardware security features in Intel SGX and ARM TrustZone[C]//Proc of the 2nd Int Conf on Communication, Computing and Digital systems. Piscataway, NJ: IEEE, 2019: 299−304
    [19]
    Ragab H, Milburn A, Razavi K, et al. Crosstalk: Speculative data leaks across cores are real[C]//Proc of the 2021 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2021: 1852−1867
    [20]
    Weisse O, Van Bulck J, Minkin M, et al. Foreshadow-NG: Breaking the virtual memory abstraction with transient out-of-order execution [EB/OL]. 2018 [2023-11-29]. https://lirias.kuleuven.be/2089352
    [21]
    Schwarz M, Schwarzl M, Lipp M, et al. Netspectre: Read arbitrary memory over network[C]//Proc of the 24th European Symp on Research in Computer Security. Berlin: Springer, 2019: 279−299
    [22]
    Stecklina J, Prescher T. Lazyfp: Leaking fpu register state using microarchitectural side-channels[J]. arXiv preprint, arXiv: 1806.07480, 2018
    [23]
    Moghimi D. Downfall: Exploiting speculative data gathering[C]//Proc of the 32nd USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2023: 7179−7193
    [24]
    Intel. Snoop assisted L1D sampling advisory [EB/OL]. (2021-05-11) [2023-11-29]. https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00330.html
    [25]
    Intel. Snoop-assisted L1 data sampling [EB/OL]. (2020-3-10) [2023-11-29]. https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/snoop-assisted-l1-data-sampling.html
    [26]
    苗新亮,蒋烈辉,常瑞. 访问驱动下的Cache侧信道攻击研究综述[J]. 计算机研究与发展,2020,57(4):824−835

    Miao Xinliang, Jiang Liehui, Chang Rui. Survey of access-driven cache-based side channel attack[J]. Journal of Computer Research and Development, 2020, 57(4): 824−835 (in Chinese)
    [27]
    张伟娟,白璐,凌雨卿,等. 缓存侧信道攻击与防御[J]. 计算机研究与发展,2023,60(1):206−222

    Zhang Weijuan, Bai Lu, Ling Yuqing, et al. Cache side-channel attacks and defenses[J]. Journal of Computer Research and Development, 2023, 60(1): 206−222(in Chinese)
    [28]
    吴晓慧,贺也平,马恒太,等. 微架构瞬态执行攻击与防御方法[J]. 软件学报,2020,31(2):544−563

    Wu XiaoHui, He Yeping, Ma Hengtai, et al. Microarchitectural transient execution attacks and defense methods[J]. Journal of Software, 2020, 31(2): 544−563(in Chinese)
    [29]
    李晔,李沛南,赵路坦,等. 瞬态执行漏洞攻击及防御综述[J]. 高技术通讯,2020,30(8):774−782

    Li Ye, Li Peinan, Zhao Lutan, et al. Overview of transient execution vulnerability attacks and defenses[J]. High Technology Communications, 2020, 30(8): 774−782 (in Chinese)
    [30]
    Canella C, Van Bulck J, Schwarz M, et al. A systematic evaluation of transient execution attacks and defenses[C]//Proc of the 28th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2019: 249−266
    [31]
    Ragab H, Barberis E, Bos H, et al. Rage against the machine clear: A systematic analysis of machine clears and their implications for transient execution attacks[C]//Proc of the 30th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2021: 1451−1468
    [32]
    Xiong Wenjie, Szefer J. Survey of transient execution attacks and their mitigations[J]. ACM Computing Surveys, 2021, 54(3): 1−36
    [33]
    Fiolhais L, Sousa L. Transient execution attacks: A computer architect perspective[J]. ACM Computing Surveys, 2023, 56(3): 1−38
    [34]
    Intel Cor. Intel 64 and IA−32 architectures optimization reference manual volume 1[EB/OL]. (2023-09-05) [2023-11-09]. https://www.intel.com/content/www/us/en/content-details/814198/intel-64-and-ia-32-architectures-optimization-reference-manual-volume-1.html
    [35]
    Van Schaik S, Milburn A, Österlund S, et al. RIDL: Rogue in-flight data load[C]//Proc of the 2019 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2019: 88−105
    [36]
    Schwarz M, Lipp M, Moghimi D, et al. ZombieLoad: Cross-privilege-boundary data sampling[C]//Proc of the 2019 ACM SIGSAC Conf on Computer and Communications Security. New York: ACM, 2019: 753−768
    [37]
    Canella C, Genkin D, Giner L, et al. Fallout: Leaking data on meltdown-resistant CPUs[C]//Proc of the 2019 ACM SIGSAC Conf on Computer and Communications Security. New York: ACM, 2019: 769−784
    [38]
    Moghimi D, Lipp M, Sunar B, et al. Medusa: Microarchitectural data leakage via automated attack synthesis[C]//Proc of the 29th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2020: 1427−1444
    [39]
    Borrello P, Kogler A, Schwarzl M, et al. ÆPIC leak: Architecturally leaking uninitialized data from the microarchitecture[C]//Proc of the 31st USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2022: 3917−3934
    [40]
    Van Schaik S, Kwong A, Genkin D, et al. SGAxe: How SGX fails in practice [EB/OL]. 2020[2024-01-01]. https://sgaxe.com/files/SGAxe.pdf
    [41]
    VUSec Group. Addendum 1 to RIDL: Rogue In-flight data load, RIDL variant as the TSX asynchronous abort [EB/OL]. (2019-11-12)[2024-01-01]. https://mdsattacks.com/files/ridl-addendum.pdf
    [42]
    VUSec Group. Addendum 2 to RIDL: Rogue in-flight data load, vector register sampling [EB/OL]. (2020-01-27)[2023-12-28]. https://mdsattacks.com/files/ridl-addendum2.pdf
    [43]
    Van Schaik S, Minkin M, Kwong A, et al. CacheOut: Leaking data on Intel CPUs via cache evictions[C]//Proc of the 2021 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2021: 339−354
    [44]
    Van Bulck J, Moghimi D, Schwarz M, et al. LVI: Hijacking transient execution through microarchitectural load value injection[C]//Proc of the 2020 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2020: 54−72
    [45]
    Jin Yu, Qiu Pengfei, Wang Chunlu, et al. Timing the transient execution: A new side-channel attack on Intel CPUs [J]. arXiv preprint, arXiv: 2304.10877, 2023
    [46]
    Šilc J, Robic B, Ungerer T. Processor Architecture: From Dataflow to Superscalar and Beyond; with 34 Tables [M]. Berlin: Springer, 1999
    [47]
    Shen J P, Lipasti M H. Modern Processor Design: Fundamentals of Superscalar Processors[M]. Long Grove, Illinois: Waveland Press, 2013
    [48]
    Tomasulo R M. An efficient algorithm for exploiting multiple arithmetic units[J]. IBM Journal of Research and Development, 1967, 11(1): 25−33 doi: 10.1147/rd.111.0025
    [49]
    González J, González A. Speculative execution via address prediction and data prefetching[C]//Proc of the 11th Int Conf on Supercomputing. New York: ACM, 1997: 196−203
    [50]
    Denning P J. The working set model for program behavior[J]. Communications of the ACM, 1968, 11(5): 323−333 doi: 10.1145/363095.363141
    [51]
    Nagarajan V. A Primer on Memory Consistency and Cache Coherence[M]. Berlin: Springer Nature, 2022
    [52]
    Papamarcos M S, Patel J H. A low-overhead coherence solution for multiprocessors with private cache memories[C]//Proc of the 11th Annual Int Symp on Computer Architecture. New York: ACM, 1984: 348−354
    [53]
    Zahran M, Albayraktaroglu K, Franklin M. Non-inclusion property in multi-level caches revisited[J]. International Journal of Computers and Their Applications, 2007, 14(2): 99−108
    [54]
    Yan Mengjia, Sprabery R, Gopireddy B, et al. Attack directories, not caches: Side channel attacks in a non-inclusive world[C]//Proc of the 2019 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2019: 888−904
    [55]
    Guo Shengjia, Chen Yueqi, Li Peng, et al. SpecuSym: Speculative symbolic execution for cache timing leak detection[C]//Proc of the 42nd ACM/IEEE Int Conf on Software Engineering. Piscataway, NJ: IEEE, 2020: 1235−1247
    [56]
    Oleksenko O, Trach B, Silberstein M, et al. SpecFuzz: Bringing spectre-type vulnerabilities to the surface[C]//Proc of the 29th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2020: 1481−1498
    [57]
    Qi Zhenxiao, Feng Qian, Cheng Yueqiang, et al. SpecTaint: Speculative Taint analysis for discovering Spectre gadgets[C] //Proc of the 2021 Symp on Network and Distributed System Security. Piscataway, NJ: IEEE, 2021: 841−855
    [58]
    Wampler J, Martiny I, Wustrow E. ExSpectre: Hiding malware in speculative execution[C]//Proc of the 2019 Symp on Network and Distributed System Security. Piscataway, NJ: IEEE, 2019: 316−330
    [59]
    Tobah Y, Kwong A, Kang I, et al. SpecHammer: Combining spectre and Rowhammer for new speculative attacks[C] //Proc of the 2022 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2022: 681−698
    [60]
    Chen Guoxing, Chen Sanchuan, Xiao Yuan, et al. Sgxpectre: Stealing intel secrets from sgx enclaves via speculative execution[C]//Proc of the 2019 IEEE European Symp on Security and Privacy. Piscataway, NJ: IEEE, 2019: 142−157
    [61]
    Trujillo D, Wikner J, Razavi K. INCEPTION: Exposing new attack surfaces with training in transient execution[C]//Proc of the 32nd USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2023: 7303−7320
    [62]
    Maisuradze G, Rossow C. ret2spec: Speculative execution using return stack buffers[C]//Proc of the 2018 ACM SIGSAC Conf on Computer and Communications Security. New York: ACM, 2018: 2109−2122
    [63]
    Maisuradze G, Backes M, Rossow C. Dachshund: Digging for and securing against (non-) blinded constants in JIT code[C]//Proc of the 2017 Symp on Network and Distributed System Security. Piscataway, NJ: IEEE, 2017: 200−215
    [64]
    Wikner J, Razavi K. RETBLEED: Arbitrary speculative code execution with return instructions[C]//Proc of the 31st USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2022: 3825−3842
    [65]
    COMSEC Computer Security Group. Retbleed: Arbitrary speculative code execution with return instructions[EB/OL]. 2022[2023-12-30]. https://comsec.ethz.ch/research/microarch/retbleed
    [66]
    Chowdhuryy M H I, Yao Fan. Leaking secrets through modern branch predictors in the speculative world[J]. IEEE Transactions on Computers, 2021, 71(9): 2059−2072
    [67]
    Koruyeh E M, Khasawneh K N, Song C, et al. Spectre returns! Speculation attacks using the return stack buffer[C/OL] //Proc of the 12th USENIX Conf on Offensive Technologies. Berkeley, CA: USENIX Association, 2018[2024-02-13]. https://www.usenix.org/system/files/conference/woot18/woot18-paper-koruyeh.pdf
    [68]
    Bhattacharyya A, Sánchez A, Koruyeh E M, et al. SpecROP: Speculative exploitation of ROP chains[C]//Proc of the 23rd Int Symp on Research in Attacks, Intrusions and Defenses. Berkeley, CA: USENIX Association, 2020: 1−16
    [69]
    Bernstein D J. Cache-timing attacks on AES [EB/OL]. 2005[2023-12-29]. https://mimoza.marmara.edu.tr/~msakalli/cse466_09/cache timing-20050414.pdf
    [70]
    Intel Cor. Intel architecture instruction set extensions programming reference [EB/OL]. 2023[2023-11-25]. https://cdrdv2.intel.com/v1/dl/getContent/671368
    [71]
    Hammarlund P, Martinez A J, Bajwa A A, et al. Haswell: The fourth-generation intel core processor[J]. IEEE Micro, 2014, 34(2): 6−20 doi: 10.1109/MM.2014.10
    [72]
    Baidu Security. Meltdown V3c &V3r [EB/OL]. (2018-03-07) [2023-11-25]. https://anquan.baidu.com/article/143
    [73]
    Müller L. Kpti a mitigation method against meltdown[C/OL] //Proc of the 4th Wiesbaden Workshop on Advanced Microkernel Operating Systems. 2018[2024-02-13]. https://www.cs.hs-rm.de/~kaiser/events/wamos2018/wamos18-proceedings.pdf#page=43
    [74]
    State Key Laboratory of Computer Architecture. Meltdown V3z and it mitigation [EB/OL]. (2019-03-26) [2023-11-25]. http://www.carch.ac.cn/hzjl/xshd/201906/t20190628_497154.html
    [75]
    Intel. Speculative behavior of swapgs and segment registers [EB/OL]. (2019-08-06)[2023-12-21]. https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/speculative-behavior-swapgs-and-segment-registers.html
    [76]
    Luțaș A, Luțaș D. Bypassing KPTI using the speculative behavior of the SWAPGS instruction [EB/OL]. 2019[2023-12-25]. https://i.blackhat.com/eu-19/Thursday/eu-19-Lutas-Bypassing-KPTI-Using-The-Speculative-Behavior-Of-The-SWAPGS-Instruction-wp.pdf
    [77]
    The MITRE Corporation. CVE−2018−3640: Spectre variant V3a [EB/OL]. (2020-06-05)[2023-12-25]. https://cve.mitre.org/cgi-bin/cvename.cgi?name=CVE-2018-3640
    [78]
    Zheng Wei, Wu Ying, Wu Xiaoxue, et al. A survey of Intel SGX and its applications[J]. Frontiers of Computer Science, 2021, 15(1): 1−15
    [79]
    Smith J E. A study of branch prediction strategies[C]//Proc of the 25th Annual Int Symp on Computer architecture. New York: ACM, 1998: 202−215
    [80]
    O’Keeffe D, Muthukumaran D, Aublin P L, et al. Spectre attack against SGX enclave [EB/OL]. 2018[2023-12-25]. https://github.com/lsds/spectre-attack-sgx
    [81]
    Kim Y, Daly R, Kim J, et al. Flipping bits in memory without accessing them: An experimental study of DRAM disturbance errors[J]. ACM SIGARCH Computer Architecture News, 2014, 42(3): 361−372 doi: 10.1145/2678373.2665726
    [82]
    Kiriansky V, Waldspurger C. Speculative buffer overflows: Attacks and defenses[J]. arXiv preprint, arXiv: 1807.03757, 2018
    [83]
    Sternberger M. Spectre-ng: An avalanche of attacks[C/OL] //Proc of the 4th Wiesbaden Workshop on Advanced Microkernel Operating Systems. 2018[2024-02-23]. https://www.cs.hs-rm.de/~kaiser/events/wamos2018/wamos18-proceedings.pdf#page=23
    [84]
    Barberis E, Frigo P, Muench M, et al. Branch history injection: On the effectiveness of hardware mitigations against cross-privilege Spectre-v2 attacks[C] //Proc of the 31st USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2022: 971−988
    [85]
    Wiebing S, de Faveri Tron A, Bos H, et al. InSpectre Gadget: Inspecting the residual attack surface of cross-privilege Spectre v2[C/OL]//Proc of the 33rd USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2024[2024-07-25]. https://download.vusec.net/papers/inspectre_sec24.pdf
    [86]
    Bletsch T, Jiang X, Freeh V W, et al. Jump-oriented programming: A new class of code-reuse attack[C]//Proc of the 6th ACM Symp on Information, Computer and Communications Security. New York: ACM, 2011: 30−40
    [87]
    Shacham H. The geometry of innocent flesh on the bone: Return-into-libc without function calls on the x86[C]//Proc of the 14th ACM Conf on Computer and Communications Security. New York: ACM, 2007: 552−561
    [88]
    AMD Cor. Software techniques for managing speculation on AMD processors, revision 5.09. 23 [EB/OL]. (2023-05-09)[2024-01-16]. https://www.amd.com/content/dam/amd/en/documents/epyc-technical-docs/tuning-guides/software-techniques-for-managing-speculation.pdf
    [89]
    INTEL. Speculative execution side channel mitigations [EB/OL]. (2021-05-26) [2024-01-16]. https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/speculative-execution-side-channel-mitigations.html
    [90]
    Huang A S, Slavenburg G, Shen J P. Speculative disambiguation: A compilation technique for dynamic memory disambiguation[J]. ACM SIGARCH Computer Architecture News, 1994, 22(2): 200−210 doi: 10.1145/192007.192012
    [91]
    Intel. Speculative store bypass [EB/OL]. (2018-5-21)[2023-12-30]. https://www.intel.cn/content/www/cn/zh/developer/articles/technical/software-security-guidance/advisory-guidance/speculative-store-bypass.html
    [92]
    Van de Pol J, Smart N P, Yarom Y. Just a little bit more[C]//Proc of the 2015 Cryptographers’ Track at the RSA Conf on Topics in Cryptology. Berlin: Springer, 2015: 3−21
    [93]
    Benger N, Van de Pol J, Smart N P, et al. “Ooh Aah. Just a Little Bit”: A small amount of side channel can go a long way[C]//Proc of the 16th Int Workshop on Cryptographic Hardware and Embedded Systems. Berlin: Springer, 2014: 75−92
    [94]
    Percival C. Cache missing for fun and profit [EB/OL]. 2005[2023-12-29]. https://css.csail.mit.edu/6.858/2014/readings/ht-cache.pdf
    [95]
    Hund R, Willems C, Holz T. Practical timing side channel attacks against kernel space ASLR[C]//Proc of the 2013 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2013: 191−205
    [96]
    Neve M, Seifert J P. Advances on access-driven cache attacks on AES[C]//Proc of the 13th Int Workshop on Selected Areas in Cryptography. Berlin: Springer, 2007: 147−162
    [97]
    Aciiçmez O. Yet another microarchitectural attack: Exploiting I-cache[C]//Proc of the 2007 ACM Workshop on Computer Security Architecture. New York: ACM, 2007: 11−18
    [98]
    Kayaalp M, Abu-Ghazaleh N, Ponomarev D, et al. A high-resolution side-channel attack on last-level cache[C] //Proc of the 53rd Annual Design Automation Conf. New York: ACM, 2016[2024-02-16]. https://doi.org/10.1145/2897937.2897962
    [99]
    Brasser F, Müller U, Dmitrienko A, et al. Software grand exposure: SGX cache attacks are practical[C]//Proc of the 11th USENIX Conf on Offensive Technologies. Berkeley, CA: USENIX Association, 2017: 11−11
    [100]
    Schwarz M, Weiser S, Gruss D, et al. Malware guard extension: Using SGX to conceal cache attacks[C]//Proc of the 14th Int Conf on Detection of Intrusions and Malware, and Vulnerability Assessment. Berlin: Springer, 2017: 3−24
    [101]
    Irazoqui G, Inci M S, Eisenbarth T, et al. Wait a minute! A fast, Cross-VM attack on AES[C]//Proc of the 17th Int Symp on Research in Attacks, Intrusions and Defenses. Berkeley, CA: USENIX Association, 2014: 299−319
    [102]
    Allan T, Brumley B B, Falkner K, et al. Amplifying side channels through performance degradation[C]//Proc of the 32nd Annual Conf on Computer Security Applications. New York: ACM, 2016: 422−435
    [103]
    Zhang Yinqian, Juels A, Reiter M K, et al. Cross-tenant side-channel attacks in PaaS clouds[C]//Proc of the 2014 ACM SIGSAC Conf on Computer and Communications Security. New York: ACM, 2014: 990−1003
    [104]
    Irazoqui G, Inci M S, Eisenbarth T, et al. Lucky 13 strikes back[C]//Proc of the 10th ACM Symp on Information, Computer and Communications Security. New York: ACM, 2015: 85−96
    [105]
    Irazoqui G, Eisenbarth T, Sunar B. Cross processor cache attacks[C]//Proc of the 11th ACM on Asia Conf on Computer and Communications Security. New York: ACM, 2016: 353−364
    [106]
    Gruss D, Spreitzer R, Mangard S. Cache template attacks: Automating attacks on inclusive last-level caches[C]//Proc of the 24th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2015: 897−912
    [107]
    Depoix J, Altmeyer P. Detecting spectre attacks by identifying cache side-channel attacks using machine learning [C/OL] //Proc of the 4th Wiesbaden Workshop on Advanced Microkernel Operating Systems. 2018[2024-01-23]. https://www.betriebssysteme.org/wp-content/uploads/2018/10/WAMOS_2018_paper_12.pdf
    [108]
    Ahmad B A. Real time detection of spectre and meltdown attacks using machine learning [J]. arXiv preprint, arXiv: 2006.01442, 2020
    [109]
    Panda B. Fooling the sense of cross-core last-level cache eviction based attacker by prefetching common sense[C]//Proc of the 28th Int Conf on Parallel Architectures and Compilation Techniques. New York: ACM, 2019: 138−150
    [110]
    Almeida J B, Barbosa M, Barthe G, et al. Verifying constant-time implementations[C]//Proc of the 25th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2016, 16: 53−70
    [111]
    Lee S, Shih M W, Gera P, et al. Inferring fine-grained control flow inside SGX enclaves with branch shadowing[C]//Proc of the 26th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2017: 557−574
    [112]
    Van Bulck J, Piessens F, Strackx R. SGX-Step: A practical attack framework for precise enclave execution control[C] //Proc of the 2nd Workshop on System Software for Trusted Execution. New York: ACM, 2017[2024-02-14]. https://doi.org/10.1145/3152701.3152706
    [113]
    Intel Cor. Intel Feature documentation: Indirect branch restricted speculation [EB/OL]. (2018-01-03)[2024-01-15]. https://www.intel.com/content/www/us/en/developer/articles/technical/software-security-guidance/technical-documentation/indirect-branch-restricted-speculation.html
    [114]
    Intel Cor. Intel Feature documentation: Single thread indirect branch predictors [EB/OL]. (2018-01-03)[2024-01-15]. https://www.intel.cn/content/www/cn/zh/developer/articles/technical/software-security-guidance/technical-documentation/single-thread-indirect-branch-predictors.html
    [115]
    Intel Cor. Intel Feature documentation: Indirect branch predictor barrier [EB/OL]. (2018-01-03)[2024-01-15]. https://www.intel.cn/content/www/cn/zh/developer/articles/technical/software-security-guidance/technical-documentation/indirect-branch-predictor-barrier.html
    [116]
    Weber D, Thomas F, Gerlach L, et al. Indirect meltdown: Building novel side-channel attacks from transient-execution attacks[C] //Proc of the 28th European Symp on Research in Computer Security. Berlin: Springer Nature, 2023: 22−42
    [117]
    Gruss D, Lipp M, Schwarz M, et al. Kaslr is dead: Long live kaslr[C]//Proc of the 9th Int Symp on Engineering Secure Software and Systems, Berlin: Springer, 2017: 161−176
    [118]
    LWN Net. Jonathan corbet: A page-table isolation update [EB/OL] (2018-04-25)[2024-02-21]. https://lwn.net/Articles/752621/
    [119]
    Hertogh M, Wiesinger M, Osterlund S, et al. Quarantine: Mitigating transient execution attacks with physical domain isolation[C]//Proc of the 26th Int Symp on Research in Attacks, Intrusions and Defenses. New York: ACM, 2023: 207−221
    [120]
    Zeller A, Gopinath R, Böhme M, et al. The fuzzing book [EB/OL]. 2019[2024-02-15]. https://publications.cispa.saarland/3120/1/index.html
    [121]
    Hur J, Song S, Kim S, et al. SpecDoctor: Differential fuzz testing to find transient execution vulnerabilities[C]//Proc of the 2022 ACM SIGSAC Conf on Computer and Communications Security. New York: ACM, 2022: 1473−1487
    [122]
    Guarnieri M, Köpf B, Morales J F, et al. Spectector: Principled detection of speculative information flows[C]//Proc of the 2020 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2020: 1−19
    [123]
    Oleksenko O, Guarnieri M, Köpf B, et al. Hide and seek with spectres: Efficient discovery of speculative information leaks with random testing[C]//Proc of the 2023 IEEE Symp on Security and Privacy. Piscataway, NJ: IEEE, 2023: 1737−1752
    [124]
    Wang Guanhua, Chattopadhyay S, Gotovchits I, et al. oo7: Low-overhead defense against spectre attacks via program analysis[J]. IEEE Transactions on Software Engineering, 2019, 47(11): 2504−2519
    [125]
    Johannesmeyer B, Koschel J, Razavi K, et al. Kasper: Scanning for generalized transient execution gadgets in the Linux kernel [C/OL] //Proc of the 2022 Network and Distributed System Security Symp. Piscataway, NJ: IEEE, 2022 [2024-02-16]. https://www.ndss-symposium.org/ndss-paper/auto-draft-247
    [126]
    Chen Yun, Hajiabadi A, Carlson T E. GADGETSPINNER: A new transient execution primitive using the loop stream detector[C]//Proc of the 2024 IEEE Int Symp on High-Performance Computer Architecture. Piscataway, NJ: IEEE, 2024: 15−30
    [127]
    Pinto S, Santos N. Demystifying arm trustzone: A comprehensive survey[J]. ACM Computing Surveys, 2019, 51(6): 1−36
    [128]
    AMD Cor. AMD secure encrypted virtualization (SEV) [EB/OL]. 2023[2024-01-25]. https://www.amd.com/zh-cn/developer/sev.html
    [129]
    RISC-V International. The RISC-V instruction set manual [EB/OL]. (2017-05-07)[2024-01-25]. https://riscv.org/wp-content/uploads/2017/05/riscv-privileged-v1.10.pdf
    [130]
    Hetterich L, Schwarz M. Branch different-spectre attacks on Apple silicon[C]//Proc of the 2022 Int Conf on Detection of Intrusions and Malware, and Vulnerability Assessment. Berlin: Springer, 2022: 116−135
    [131]
    Wu Minjun, McCamant S, Yew P C, et al. PREDATOR: A cache side-channel attack detector based on precise event monitoring[C]//Proc of the 2022 IEEE Int Symp on Secure and Private Execution Environment Design. Piscataway, NJ: IEEE, 2022: 25−36
    [132]
    Townley D, Arıkan K, Liu Y D, et al. Composable cachelets: Protecting enclaves from cache side-channel Attacks[C]//Proc of the 31st USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2022: 2839−2856
    [133]
    Yan Hui, Cui Chaoyuan. CacheHawkeye: Detecting cache side channel attacks based on memory events[J]. Future Internet, 2022, 14(1): 24−36 doi: 10.3390/fi14010024
    [134]
    Luo Mulong, Xiong Wenjie, Lee G, et al. Autocat: Reinforcement learning for automated exploration of cache-timing attacks[C] //Proc of the 2023 IEEE Int Symp on High-Performance Computer Architecture. Piscataway, NJ: IEEE, 2023: 317−332
    [135]
    Evers M, Barnes L, Clark M. The AMD next-generation “Zen 3” core[J]. IEEE Micro, 2022, 42(3): 7−12 doi: 10.1109/MM.2022.3152788
    [136]
    Purnal A, Turan F, Verbauwhede I. Double trouble: Combined heterogeneous attacks on non-inclusive cache hierarchies[C] //Proc of the 31st USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2022: 3647−3664
    [137]
    Popescu M C, Balas V E, Perescu-Popescu L, et al. Multilayer perceptron and neural networks[J]. WSEAS Transactions on Circuits and Systems, 2009, 8(7): 579−588
    [138]
    Sönmez B, Sarıkaya A A, Bahtiyar Ş. Machine learning based side channel selection for time-driven cache attacks on AES[C] //Proc of the 4th Int Conf on Computer Science and Engineering. New York: ACM, 2019[2024-02-17]. https://doi.org/10.1109/UBMK.2019.8907211
    [139]
    Ding Ruyi, Zhang Ziyue, Zhang Xiang, et al. A cross-platform cache timing attack framework via deep learning[C]//Proc of the 2022 Design, Automation & Test in Europe Conf & Exhibition. Piscataway, NJ: IEEE, 2022: 676−681
    [140]
    Tol M C, Gulmezoglu B, Yurtseven K, et al. FastSpec: Scalable generation and detection of spectre gadgets using neural embeddings[C]//Proc of the 2021 IEEE European Symp on Security and Privacy. Piscataway, NJ: IEEE, 2021: 616−632
    [141]
    Zhang Quanjun, Fang Chunrong, Yu Bowen, et al. Pre-trained model-based automated software vulnerability repair: How far are we?[J]. IEEE Transactions on Dependable and Secure Computing, 2024, 21(4): 2507−2525 doi: 10.1109/TDSC.2023.3308897
    [142]
    Fustos J, Farshchi F, Yun H. Spectreguard: An efficient data-centric defense mechanism against spectre attacks [C/OL] //Proc of the 56th Annual Design Automation Conf. New York: ACM, 2019[2024-02-11]. https://dl.acm.org/doi/pdf/10.1145/3316781.3317914
    [143]
    Loughlin K, Neal I, Ma Jiacheng, et al. DOLMA: Securing speculation with the principle of transient Non-Observability[C]//Proc of the 30th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2021: 1397−1414
    [144]
    Werner M, Unterluggauer T, Giner L, et al. ScatterCache: Thwarting cache attacks via cache set randomization[C]//Proc of the 28th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2019: 675−692
    [145]
    Bandara S, Kinsy M A. Adaptive caches as a defense mechanism against cache side-channel attacks[C]//Proc of the 3rd ACM Workshop on Attacks and Solutions in Hardware Security Workshop. New York: ACM, 2019: 55−64
    [146]
    García C P, Brumley B B. Constant-time callees with variable-time callers[C]//Proc of the 26th USENIX Conf on Security Symp. Berkeley, CA: USENIX Association, 2017: 83−98
    [147]
    Qiu Pengfei, Gao Qiang, Wang Dongsheng, et al. PMU-Leaker: Performance monitor unit-based realization of cache side-channel attacks[C]//Proc of the 28th Asia and South Pacific Design Automation Conf. 2023: 664−669
  • Related Articles

    [1]Li Junwei, Liu Quan, Huang Zhigang, Xu Yapeng. A Diversity-Enriched Option-Critic Algorithm with Interest Functions[J]. Journal of Computer Research and Development, 2024, 61(12): 3108-3120. DOI: 10.7544/issn1000-1239.202220970
    [2]Zhao Rongmei, Sun Siyu, Yan Fanli, Peng Jian, Ju Shenggen. Multi-Interest Aware Sequential Recommender System Based on Contrastive Learning[J]. Journal of Computer Research and Development, 2024, 61(7): 1730-1740. DOI: 10.7544/issn1000-1239.202330622
    [3]Zhu Haiping, Wang Ziyu, Zhao Chengcheng, Chen Yan, Liu Jun, Tian Feng. Learning Resource Recommendation Method Based on Spatio-Temporal Multi-Granularity Interest Modeling[J]. Journal of Computer Research and Development. DOI: 10.7544/issn1000-1239.202440249
    [4]Liu Haijiao, Ma Huifang, Zhao Qiqi, Li Zhixin. Target Community Detection with User Interest Preferences and Influence[J]. Journal of Computer Research and Development, 2021, 58(1): 70-82. DOI: 10.7544/issn1000-1239.2021.20190775
    [5]Guo Kaihong, Han Hailong. Personalized Recommendation Model Based on Quantifier Induced by Preference[J]. Journal of Computer Research and Development, 2020, 57(1): 124-135. DOI: 10.7544/issn1000-1239.2020.20190166
    [6]Gao Ling, Gao Quanli, Wang Hai, Wang Wei, Yang Kang. A Preference Prediction Method Based on the Optimization of Basic Similarity Space Distribution[J]. Journal of Computer Research and Development, 2018, 55(5): 977-985. DOI: 10.7544/issn1000-1239.2018.20160924
    [7]Guo Chi, Wang Lina, Guan Yiping, Zhang Xiaoying. A Network Immunization Strategy Based on Dynamic Preference Scan[J]. Journal of Computer Research and Development, 2012, 49(4): 717-724.
    [8]Zou Bowei, Zhang Yu, Fan Jili, Zheng Wei, and Liu Ting. Research on Personalized Information Retrieval Based on User’s New Interest Detection[J]. Journal of Computer Research and Development, 2009, 46(9): 1594-1600.
    [9]Wang Zhenzhen, Xing Hancheng, and Chen Hanwu. On a Preference System of Agent and Its Construction[J]. Journal of Computer Research and Development, 2009, 46(2): 253-260.
    [10]Wu Jing, Zhang Pin, Luo Xin, Sheng Hao, and Xiong Zhang. Mining Interests and Navigation Patterns in Personalization on Portal[J]. Journal of Computer Research and Development, 2007, 44(8): 1284-1292.

Catalog

    Article views (130) PDF downloads (50) Cited by()

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return