• 中国精品科技期刊
  • CCF推荐A类中文期刊
  • 计算领域高质量科技期刊T1类
Advanced Search
Lai Yuanming, Li Yalong, Hu Hanzhi, Xie Mengyao, Wang Zhe, Wu Chenggang. SIMD-RVV Dynamic Binary Translation Optimization: Redundant Configuration Elimination and Hybrid Translation-Driven Cross-Architecture Programming Model Adaptation[J]. Journal of Computer Research and Development. DOI: 10.7544/issn1000-1239.202550135
Citation: Lai Yuanming, Li Yalong, Hu Hanzhi, Xie Mengyao, Wang Zhe, Wu Chenggang. SIMD-RVV Dynamic Binary Translation Optimization: Redundant Configuration Elimination and Hybrid Translation-Driven Cross-Architecture Programming Model Adaptation[J]. Journal of Computer Research and Development. DOI: 10.7544/issn1000-1239.202550135

SIMD-RVV Dynamic Binary Translation Optimization: Redundant Configuration Elimination and Hybrid Translation-Driven Cross-Architecture Programming Model Adaptation

More Information
  • Author Bio:

    Lai Yuanming: born in 1991. PhD candidate. His main research interests include binary translation, computer systems security, and code obfuscation. (laiyuanming@ict.ac.cn)

    Li Yalong: born in 2000. Master candidate. His main research interests include binary translation optimization and RISC-V architecture. (li2542369686@163.com)

    Hu Hanzhi: born in 1999. Master candidate. His main research interests include binary translator optimization and compiler optimization. (huhanzhi22s@ict.ac.cn)

    Xie Mengyao: born in 1992. PhD, Associate professor, master supervisor. Her main research interests include computer system architecture and system security

    Wang Zhe: born in 1990. PhD, associate Professor, master supervisor. Member of CCF. His main research interests include computer systems security, operating systems, and computer architecture

    Wu Chenggang: born in 1969. PhD, professor, PhD supervisor. Distinguished member of CCF. His main research interests include binary translation, compiler optimization, and computer systems security. (wucg@ict.ac.cn)

  • Received Date: February 28, 2025
  • Revised Date: April 08, 2025
  • Available Online: April 16, 2025
  • RISC-V, renowned for its open-source nature and modular design, has achieved remarkable success in embedded systems and is progressively expanding into the high-performance computing (HPC) domain. While RISC-V hardware tailored for HPC, such as the Sophon SG2042 multi-core processors, has demonstrated performance level comparable to X86/ARM counterparts, its underdeveloped software ecosystem remains a critical barrier to broader adoption. To address this challenge, we developed RVBT, a process-level dynamic binary translator for RISC-V, designed to bridge the software gap by efficiently porting the mature X86 ecosystem to RISC-V platforms, thereby accelerating RISC-V’s integration into HPC applications. Focusing on the pervasive use of SIMD instructions in HPC programs, this study tackles the inefficiencies arising from fundamental differences in programming models between X86 SIMD and RISC-V Vector (RVV) extensions. Specifically, X86 SIMD hardcodes data types within opcodes, whereas RVV dynamically configures vtype and mask registers, leading to redundant operations during direct translation. To overcome this, we propose three innovative optimizations to achieve: 1) Redundancy elimination via data type locality. By leveraging the locality of data types in adjacent SIMD operations, we statically analyze and remove redundant configurations of vtype (achieving 100% dynamic elimination rates for csrr and vsetvl, and 56.31% for vsetvli) and mask settings (74.66% elimination rate in floating-point benchmarks). 2) Hybrid translation with on-demand synchronization. We decouple scalar and vectorized floating-point operations, translating X86 SIMD scalar double-precision instructions to RISC-V’s floating-point extensions and reserving RVV for vectorized operations. Data synchronization between scalar and vector registers is optimized through defuse analysis, achieving a 67.35% dynamic synchronization reduction in floating-point benchmarks. Experimental results on SPEC CPU 2006 demonstrate significant improvements on the optimized RVBT achieves 47.39% and 40.06% of native execution efficiency for integer and floating-point benchmarks, respectively, representing speedups of 1.21× and 8.31× over the unoptimized version. RVBT vastly outperforms QEMU (18.84% and 4.81% for integer and floating-point), with floating-point efficiency surpassing QEMU by 8.33 times, highlighting its potential for deployment in certain HPC scenarios. Crucially, these optimizations are architecture-agnostic: The methodology of exploiting data type locality, hybrid instruction translation, and adaptive synchronization apply equally to ARM SIMD (e.g., NEON) to RVV translation, offering a universal framework for cross-ISA binary compatibility. This work provides a pivotal technical foundation for breaking the software ecosystem deadlock and advancing RISC-V’s role in HPC.

  • [1]
    Waterman A, Lee Y, Patterson D A, et al. The RISC-V instruction set manual, volume I: user-level ISA, version 2.0[J]. EECS Department, University of California, Berkeley, Tech. Rep. UCB/EECS−2014−54, 2014: 4
    [2]
    Li Chunqiang, Liu Zhiwei, Shang Yunhai, et al. A hardware non-invasive mapping method for condition bits in binary translation[J]. Electronics, 2023, 12(14): 3014 doi: 10.3390/electronics12143014
    [3]
    RISC-V International. There Will Be 62.4 Billion RISC-V Processor Cores in Operation by 2025[EB/OL]. (2020-04-02)[2024-11-12]. https://riscv.org/ecosystem-news/2020/04/there-will-be-62-4-billion-risc-v-processor-cores-in-operation-by-2025-francois-gauthier-lembarque
    [4]
    Weaver D, McIntosh-Smith S. An empirical comparison of the RISC-V and AArch64 instruction sets[C]//Proc of the SC’23 Workshops of the Int Conf on High Performance Computing, Network, Storage, and Analysis. New York, NY, USA: ACM, 2023: 1557−1565
    [5]
    Xi Wang, Leidel J D, Williams B, et al. Xbgas: a global address space extension on RISC-V for high performance computing[C]//Proc of 2021 IEEE Int Parallel and Distributed Processing Symposium (IPDPS). Piscataway, NJ: IEEE, 2021: 454−463
    [6]
    Borja Perez, Alexander Fell, John D. Davis. Coyote: an open source simulation tool to enable RISC-V in HPC[C]//Proc of 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE). Piscataway, NJ: IEEE, 2021: 130−135
    [7]
    Andrea Bartolini, Federico Ficarelli, Emanuele Parisi, et al. Monte cimone: paving the road for the first generation of RISC-V high-performance computers[C]//Proc of 2022 IEEE 35th Int System-on-Chip Conference (SOCC). Piscataway, NJ: IEEE, 2022: 1−6
    [8]
    Chen Chen, Xiang Xiaoyan, Liu Chang, et al. Xuantie−910: A commercial multi-core 12-stage pipeline out-of-order 64-bit high performance RISC-V processor with vector extension: industrial product[C]//Proc of 2020 ACM/IEEE 47th Annual Int Symp on Computer Architecture (ISCA). Piscataway, NJ: IEEE, 2020: 52−64
    [9]
    Nick Brown, Maurice Jamieson. Performance characterisation of the 64-core sg2042 RISC-V CPU for HPC[C]//Proc of Int Conf on High Performance Computing. Berlin: Springer, 2025: 354−367
    [10]
    北京开源芯片研究院. 2024中关村论坛10项重大科技成果——第三代“香山”开源高性能RISC-V处理器核对外发布. [EB/OL]. (2024-04-25)[2024-11-12]. https://www.bosc.ac.cn/newsinfo/7105467.html?templateId=564439
    [11]
    Nick Brown, Maurice Jamieson, Joseph Lee, et al. Is RISC-V ready for HPC prime-time: evaluating the 64-core sophon sg2042 RISC-V CPU[C]//Proc of the SC’23 Workshops of the Int Conf on High Performance Computing, Network, Storage, and Analysis. New York: ACM, 2023: 1566−1574
    [12]
    Sophon. Milk-V Pioneer Board. [EB/OL]. [2024-11-12]. https://sophon-static.sophon.cn/product/introduce/pioneerBoard.html
    [13]
    Xuantie. 如意BOOK甲辰版. [EB/OL]. [2024-11-12]. https://www.xrvm.cn/product/xuantie/4321312678808195072
    [14]
    Vedran Dakić, Leo Mršić, Zdravko Kunić, et al. Evaluating ARM and RISC-V architectures for high-performance computing with docker and kubernetes[J]. Electronics, 2024, 13(17): 3494 doi: 10.3390/electronics13173494
    [15]
    Ramon Canal, Stefano Di Carlo, Dimitris Gizopoulos, et al. Vitamin-V: expanding open-source RISC-V cloud environments[J]. arXiv preprint, arXiv: 2407.00052, 2024
    [16]
    Ramon Canal, Cristiano Chenet, Angelos Arelakis, et al. Vitamin-V: virtual environment and tool-boxing for trustworthy development of RISC-V based cloud services[C]//Proc of the 26th Euromicro Conf on Digital System Design (DSD). Piscataway, NJ: IEEE, 2023: 302−308
    [17]
    Nick Brown. RISC-V for HPC: Where we are and where we need to go[J]. arXiv preprint, arXiv: 2406.12398, 2024
    [18]
    Jasmina Saidova. RISC-V architecture and its role in the near future[J]. Journal of Advanced Scientific Research (ISSN: 0976−9595), 2024, 5(9
    [19]
    陈龙,武成岗,谢海斌,等. 二进制翻译中解析多目标分支语句的图匹配方法[J]. 计算机研究与发展,2008,45(10):1789−1798

    Chen Long, Wu ChenggangG, Xie HaibinB, et al. Graph matching method for parsing multi-target branching sentences in binary translation[J]. Journal of Computer Research and Development, 2008, 45(10): 1789−1798 (in Chinese)
    [20]
    杨浩,唐锋,谢海斌,等. 二进制翻译中的库函数处理[J]. 计算机研究与发展,2006,43(12):2174−2179

    Yang Hao, Tang Feng, Xie Haibin, et al. Library function processing in binary translation[J]. Journal of Computer Research and Development, 2006, 43(12): 2174−2179 (in Chinese).
    [21]
    唐锋,武成岗,张兆庆,等. 二进制翻译应用级异常处理[J]. 计算机研究与发展,2006,43(12):2166−2173

    Tang Feng, Wu Chenggang, Zhang Zhaoqing, et al. Binary translation application level exception handling[J]. Journal of Computer Research and Development, 2006, 43(12): 2166−2173 (in Chinese).
    [22]
    谢汶兵,田雪,漆锋滨,等. 二进制翻译技术综述[J]. 软件学报,2024,35(6):2687−2723

    Xie Wenbing, Tian Xue, Qi Fengbin, et al. A review of binary translation technology[J]. Ruan Jian Xue Bao/Jouinal of Software, 2024, 35(6): 2687−2723 (in Chinese)
    [23]
    Li Jianjun, Wu Chenggang, Hsu Wei-Chung. Efficient and effective misaligned data access handling in a dynamic binary translation system[J]. ACM Transactions on Architecture and Code Optimization, 2011, 8(2): 1−29
    [24]
    Li Jianjun, Wu Chenggang, Hsu Wei-Chung. An evaluation of misaligned data access handling mechanisms in dynamic binary translation systems[C]//Proc of 2009 Int Symp on Code Generation and Optimization. Piscataway, NJ: IEEE, 2009: 180−189
    [25]
    唐锋,武成岗,冯晓兵,等. 基于动态反馈的标志位线性分析算法[J]. 软件学报,2007(7):1603−1611

    Tang Feng, Wu Chenggang, Feng Xiaobing, et al. Marker linear analysis algorithm based on dynamic feedback[J]. Jouinal of Software, 2007(7): 1603−1611 (in Chinese)
    [26]
    Fabrice Bellard. QEMU, a fast and portable dynamic translator[C]//Proc of Usenix Annual Technical Conf, Freenix Track. Berkeley, CA: USENIX Association, 2005, 41(46): 10−5555
    [27]
    Xie Benyi, Yan Yue, Yan Chenghao, et al. An instruction inflation analyzing framework for dynamic binary translators[J]. ACM Transactions on Architecture and Code Optimization, 2024, 21(2): 1−25
    [28]
    Evangelos Georganas, Sasikanth Avancha, Kunal Banerjee, et al. Anatomy of high-performance deep learning convolutions on SIMD architectures[C]//Proc of SC18: Int Conf for High Performance Computing, Networking, Storage and Analysis. Piscataway, NJ: IEEE, 2018: 830−841
    [29]
    Zhang Jiyuan, Franz Franchetti, Tze Meng Low. High performance zero-memory overhead direct convolutions[C/OL]//Proc of Intl Conf on Machine Learning. 2018[2024-11-12]. https://proceedings.mlr.press/v80/zhang18d.html
    [30]
    Daon Park, Bernhard Egger. Improving throughput-oriented LLM inference with cpu computations[C]//Proc of the 2024 Int Conf on Parallel Architectures and Compilation Techniques. New York: ACM, 2024: 233−245
    [31]
    Haihao Shen, Hanwen Chang, Bo Dong, et al. Efficient LLM inference on cpus[J]. arXiv preprint, arXiv: 2311.00502, 2023
    [32]
    Haihao Shen, Hengyu Meng, Bo Dong, et al. An efficient sparse inference software accelerator for transformer-based language models on cpus[J]. arXiv preprint, arXiv: 2306.16601, 2023
    [33]
    Xuanlin Jiang, Yang Zhou, Shiyi Cao, et al. Neo: Saving GPU memory crisis with CPU offloading for online LLM inference[J]. arXiv preprint, arXiv: 2411.01142, 2024
    [34]
    Gary Bradski. The opencv library[J]. Dr. Dobb’s Journal: Software Tools for the Professional Programmer, 2000, 25(11): 120−123
    [35]
    Suramya Tomar. Converting video formats with ffmpeg[J]. Linux Journal, 2006, 2006(146): 10
    [36]
    Shuja J, Gani A, ur Rehman M H, et al. Towards native code offloading based mcc frameworks for multimedia applications: A survey[J]. Journal of Network and Computer Applications, 2016, 75: 335−354 doi: 10.1016/j.jnca.2016.08.021
    [37]
    Amogh Akshintala, Bhushan Jain, Chia-Che Tsai, et al. X86−64 instruction usage among c/c++ applications[C]//Proc of the 12th ACM Int Conf on Systems and Storage. New York: ACM, 2019: 68−79
    [38]
    Emilio G. Cota, Luca P. Carloni. Cross-ISA machine instrumentation using fast and scalable dynamic binary translation[C]//Proc of the 15th ACM SIGPLAN/SIGOPS Int Conf on Virtual Execution Environments. New York: ACM, 2019: 74−87
    [39]
    PtitSeb. Box64[EB/OL]. [2024-11-12]. https://github.com/ptitSeb/box64
    [40]
    余子濠,陈璐,孙凝晖,等. 以RISC-V为目标的动态二进制翻译代码质量优化方法[J]. 计算机研究与发展,2023,60(10):2322−2334 doi: 10.7544/issn1000-1239.202220296

    Yu Zihao, Chen Lu, Shun Ninghui, et al. Dynamic binary translation code quality optimization method targeting RISC-V[J]. Journal of Computer Research and Development, 2023, 60(10): 2322−2334 (in Chinese). doi: 10.7544/issn1000-1239.202220296
    [41]
    Zhaoxin Yang, Xuehai Chen, Liangpu Wang, et al. MFHBT: hybrid binary translation system with multi-stage feedback powered by LLVM[C]//Proc of Int Symp on Advanced Parallel Processing Technologies. Berlin: Springer, 2023: 310−325
    [42]
    A Chernoff, R Hookway. DIGITAL FX! 32 running 32-Bit x86 applications on Alpha NT[C]//Proc of Large-Scale System Administration of Windows NT Workshop (Large-Scale System Administration of Windows NT Workshop). Berkeley, CA: USENIX Associatio, 1997
    [43]
    Fu Sheng-Yu, Hong Ding-Yong, Liu Yu-Ping, et al. Efficient and retargetable SIMD translation in a dynamic binary translator[J]. Software: Practice and Experience, 2018, 48(6): 1312−1330 doi: 10.1002/spe.2573
    [44]
    Amanieu D’Antras, Cosmin Gorgovan, Jim Garside, et al. Low overhead dynamic binary translation on ARM[C]//Proc of the 38th ACM SIGPLAN Conf on Programming Language Design and Implementation. New York: ACM, 2017: 333−346
    [45]
    Hong Ding-Yong, Fu Sheng-Yu, Liu Yu-Ping, et al. Exploiting longer SIMD lanes in dynamic binary translation[C]//Proc of 2016 IEEE 22nd Int Conf on Parallel and Distributed Systems (ICPADS). Piscataway, NJ: IEEE, 2016: 853−860
    [46]
    马湘宁,武成岗,唐锋,等. 二进制翻译中的标志位优化技术[J]. 计算机研究与发展,2005,42(2):329−337 doi: 10.1360/crad20050222

    Ma Xiangning, Wu Chenggang, Tang Feng, et al. Flag bit optimization technology in binary translation[J]. Journal of Computer Research and Development, 2005, 42(2): 329−337 (in Chinese). doi: 10.1360/crad20050222
    [47]
    王文文,武成岗,白童心,等. 二进制翻译中标志位的模式化翻译方法[J]. 计算机研究与发展,2014,51(10):2336−2347

    Wang Wenwen, Wu Chenggang, Bai Tongxin, et al. Patterned translation method of flag bits in binary translation[J]. Journal of Computer Research and Development, 2014, 51(10): 2336−2347 (in Chinese)
    [48]
    Hongqing Zeng, Min Xie, Yong Dong, et al. Efficient condition code emulation for dynamic binary translation systems[C]//Proc of 3rd Int Symp on Computer Engineering and Intelligent Communications (ISCEIC 2022). Bellingham, WA: SPIE, 2023, 12462: 421−432
    [49]
    Liu Yu-Ping, Hong Ding-Yong, Wu Jan-Jan, et al. Exploiting SIMD asymmetry in ARM-to-X86 dynamic binary translation[J]. ACM Transactions on Architecture and Code Optimization, 2019, 16(1): 1−24
    [50]
    Junaid Shuja, Abdullah Gani, Kwangman Ko, et al. SIMDOM: A framework for SIMD instruction translation and offloading in heterogeneous mobile architectures[J]. Transactions on Emerging Telecommunications Technologies, 2018, 29(4): e3174 doi: 10.1002/ett.3174
    [51]
    Nabil Hallou, Erven Rohou, Philippe Clauss, et al. Dynamic re-vectorization of binary code[C]//Proc of 2015 Int Conf on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS). Piscataway, NJ: IEEE, 2015: 228−237
    [52]
    Nabil Hallou, Erven Rohou & Philippe Clauss. Runtime vectorization transformations of binary code[J]. International Journal of Parallel Programming, 2017, 45: 1536−1565 doi: 10.1007/s10766-016-0480-z
    [53]
    Wu Jin, Dong Jian, Fang Ruili, et al. Effective exploitation of SIMD resources in cross-ISA virtualization[C]//Proc of the 17th ACM SIGPLAN/SIGOPS Int Conf on Virtual Execution Environments. New York: ACM, 2021: 84−97
    [54]
    Liu Yuping, Hong Dingyong, Wu Jan-Jan, et al. Exploiting asymmetric SIMD register configurations in ARM-to-X86 dynamic binary translation[C]//Proc of 2017 26th Int Conf on Parallel Architectures and Compilation Techniques (PACT). Piscataway, NJ: IEEE, 2017: 343−355
    [55]
    Lin Chih-Min, Fu Sheng-Yu, Hong Ding-Yong, et al. Exploiting vector processing in dynamic binary translation[C]//Proc of the 48th Int Conf on Parallel Processing. New York: ACM, 2019: 1−10
    [56]
    Fu Shengyu, Hong Dingyong, Liu Yuping, et al. Dynamic translation of structured loads/stores and register mapping for architectures with SIMD extensions[C]//Proc of the 18th ACM SIGPLAN/SIGBED Conf on Languages, Compilers, and Tools for Embedded Systems. New York: ACM, 2017: 31−40
    [57]
    Fu Sheng-Yu, Hong Ding-Yong, Liu Yu-Ping, et al. Optimizing data permutations in structured loads/stores translation and SIMD register mapping for a cross-ISA dynamic binary translator[J]. Journal of Systems Architecture, 2019, 98: 173−190 doi: 10.1016/j.sysarc.2019.07.008
    [58]
    Hong Ding-Yong, Fu Sheng-Yu, Liu Yu-Ping, et al. Exploiting longer SIMD lanes in dynamic binary translation[C]//Proc of 2016 IEEE 22nd Int Conf on Parallel and Distributed Systems (ICPADS). Piscataway, NJ: IEEE, 2016: 853−860
    [59]
    Hong Ding-Yong, Liu Yu-Ping, Fu Sheng-Yu, et al. Improving SIMD parallelism via dynamic binary translation[J]. ACM Transactions on Embedded Computing Systems, 2018, 17(3): 1−27
    [60]
    Luc Michel, Nicolas Fournel, Frédéric Pétrot. Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation[C]//Proc of 2011 Design, Automation & Test in Europe. Piscataway, NJ: IEEE, 2011: 1−4
    [61]
    Li Jianhui, Zhang Qi, Xu Shu, et al. Optimizing dynamic binary translation for SIMD instructions[C]//Proc of Int Symp on Code Generation and Optimization (CGO’06). Piscataway, NJ: IEEE, 2006: 12−280
    [62]
    Nathan Clark, Amir Hormati, Sami Yehia, et al. Liquid SIMD: abstracting SIMD hardware using lightweight dynamic mapping[C]//Proc of 2007 IEEE 13th Int Symp on High Performance Computer Architecture. Piscataway, NJ: IEEE, 2007: 216−227
    [63]
    Zhou Ruoyu, George Wort, Márton Erdős, et al. The janus triad: Exploiting parallelism through dynamic binary modification[C]//Proc of the 15th ACM SIGPLAN/SIGOPS Int Conf on Virtual Execution Environments. New York: ACM, 2019: 88−100
    [64]
    Takashi Nakamura, Satoshi Miki, Shuichi Oikawa. Automatic vectorization by runtime binary translation[C]//Proc of 2011 2nd Int Conf on networking and computing. Piscataway, NJ: IEEE, 2011: 87−94
    [65]
    Michael Guilherme Jordan, Tiago Knorst, Julio Vicenzi, et al. Boosting SIMD benefits through a run-time and energy efficient dlp detection[C]//Proc of 2019 Design, Automation & Test in Europe Conf & Exhibition (DATE). Piscataway, NJ: IEEE, 2019: 722−727
    [66]
    Shen Bor-Yeh, Chen Jiunn-Yeu, Hsu Wei-Chung, et al. LLBT: An LLVM-based static binary translator[C]//Proc of the 2012 Int Conf on Compilers, Architectures and Synthesis for Embedded Systems. New York ACM, 2012: 51−60
    [67]
    Martin Fink. Translating X86 Binaries to LLVM Intermediate Representation[D/OL]. 2022[2024-11-12]. https://dse.in.tum.de/wp-content/uploads/2022/01/translating_x86_binaries_into_llvm_intermediate_representation.pdf
    [68]
    Fu Sheng-Yu, Wu Jan-Jan, Hsu Wei-Chung. Improving SIMD code generation in QEMU[C]//Proc of 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE). Piscataway, NJ: IEEE, 2015: 1233−1236
    [69]
    Fu Sheng-Yu, Hong Ding-Yong, Wu Jan-Jan, et al. SIMD code translation in an enhanced hqemu[C]//Proc of 2015 IEEE 21st Int Conf on Parallel and Distributed Systems (ICPADS). Piscataway, NJ: IEEE, 2015: 507−514
    [70]
    Hong Ding-Yong, Hsu Chun-Chen, Yew Pen-Chung, et al. HQEMU: A multi-threaded and retargetable dynamic binary translator on multicores[C]//Proc of the 10th Int Symp on Code Generation and Optimization. New York: ACM, 2012: 104−113
    [71]
    谢海斌,武成岗,崔慧敏,等. 二进制翻译中的 X86 浮点栈处理[J]. 计算机研究与发展,2007,44(11):1946−1954 doi: 10.1360/crad20071119

    Xie Haibin, Wu Chenggang, Cui Huimin, et al. X86 floating point stack processing in binary translation[J]. Journal of Computer Research and Development, 2007, 44(11): 1946−1954 (in Chinese). doi: 10.1360/crad20071119
    [72]
    Wu Jin, Dong Jian, Fang Ruili, et al. Effective exploitation of SIMD resources in cross-ISA virtualization[C]//Proc of the 17th ACM SIGPLAN/SIGOPS Int Conf on Virtual Execution Environments. New York: ACM, 2021: 84−97
    [73]
    E. R. Altman, D. Kaeli, Y. Sheffer. Welcome to the opportunities of binary translation[J]. Computer, 2000, 33(3): 40−45
  • Related Articles

    [1]Li Song, Cao Wenqi, Hao Xiaohong, Zhang Liping, Hao Zhongxiao. Collective Spatial Keyword Query Based on Time-Distance Constrained and Cost Aware[J]. Journal of Computer Research and Development, 2025, 62(3): 808-819. DOI: 10.7544/issn1000-1239.202330815
    [2]Wang Kaifan, Xu Yinan, Yu Zihao, Tang Dan, Chen Guokai, Chen Xi, Gou Lingrui, Hu Xuan, Jin Yue, Li Qianruo, Li Xin, Lin Jiawei, Liu Tong, Liu Zhigang, Wang Huaqiang, Wang Huizhe, Zhang Chuanqi, Zhang Fawang, Zhang Linjuan, Zhang Zifei, Zhang Ziyue, Zhao Yangyang, Zhou Yaoyang, Zou Jiangrui, Cai Ye, Huan Dandan, Li Zusong, Zhao Jiye, He Wei, Sun Ninghui, Bao Yungang. XiangShan Open-Source High Performance RISC-V Processor Design and Implementation[J]. Journal of Computer Research and Development, 2023, 60(3): 476-493. DOI: 10.7544/issn1000-1239.202221036
    [3]Ren Hao, Liu Baisong, Sun Jinyang, Dong Qian, Qian Jiangbo. A Time and Relation-Aware Graph Collaborative Filtering for Cross-Domain Sequential Recommendation[J]. Journal of Computer Research and Development, 2023, 60(1): 112-124. DOI: 10.7544/issn1000-1239.202110545
    [4]Zhang Tong, Feng Jiaqi, Ma Yanying, Qu Siyuan, Ren Fengyuan. Survey on Traffic Scheduling in Time-Sensitive Networking[J]. Journal of Computer Research and Development, 2022, 59(4): 747-764. DOI: 10.7544/issn1000-1239.20210203
    [5]Cui Yuanning, Li Jing, Shen Li, Shen Yang, Qiao Lin, Bo Jue. Duration-HyTE: A Time-Aware Knowledge Representation Learning Method Based on Duration Modeling[J]. Journal of Computer Research and Development, 2020, 57(6): 1239-1251. DOI: 10.7544/issn1000-1239.2020.20190253
    [6]Zheng Xiao, Gao Han, Wang Xiujun, Qin Feng. Contact Duration Aware Cooperative Data Caching in Mobile Opportunistic Networks[J]. Journal of Computer Research and Development, 2018, 55(2): 338-345. DOI: 10.7544/issn1000-1239.2018.20160929
    [7]Wang Chong, Lü Yinrun, Chen Li, Wang Xiuli, Wang Yongji. Survey on Development of Solving Methods and State-of-the-Art Applications of Satisfiability Modulo Theories[J]. Journal of Computer Research and Development, 2017, 54(7): 1405-1425. DOI: 10.7544/issn1000-1239.2017.20160303
    [8]Chen Huangke, Zhu Jianghan, Zhu Xiaomin, Ma Manhao, Zhang Zhenshi. Resource-Delay-Aware Scheduling for Real-Time Tasks in Clouds[J]. Journal of Computer Research and Development, 2017, 54(2): 446-456. DOI: 10.7544/issn1000-1239.2017.20151123
    [9]Zhou Hang, Huang Zhiqiu, Zhu Yi, Xia Liang, Liu Linyuan. Real-Time Systems Contact Checking and Resolution Based on Time Petri Net[J]. Journal of Computer Research and Development, 2012, 49(2): 413-420.
    [10]Zhou Hang, Huang Zhiqiu, Hu Jun, Zhu Yi. Real-Time System Resource Conflict Checking Based on Time Petri Nets[J]. Journal of Computer Research and Development, 2009, 46(9): 1578-1585.

Catalog

    Article views (51) PDF downloads (20) Cited by()

    /

    DownLoad:  Full-Size Img  PowerPoint
    Return
    Return