Optimizing Cross-Architecture Programming Model Adaptation in SIMD-to-RVV Dynamic Binary Translation

Lai Yuanming; Li Yalong; Hu Hanzhi; Xie Mengyao; Wang Zhe; Wu Chenggang

doi:10.7544/issn1000-1239.202550135

Journal of Computer Research and Development > 2025 > Corrected proof > DOI: 10.7544/issn1000-1239.202550135 CSTR: 32373.14.issn1000-1239.202550135

Lai Yuanming, Li Yalong, Hu Hanzhi, Xie Mengyao, Wang Zhe, Wu Chenggang. Optimizing Cross-Architecture Programming Model Adaptation in SIMD-to-RVV Dynamic Binary Translation[J]. Journal of Computer Research and Development. DOI: 10.7544/issn1000-1239.202550135

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Optimizing Cross-Architecture Programming Model Adaptation in SIMD-to-RVV Dynamic Binary Translation

Lai Yuanming^{1, 2,},
Li Yalong^{1, 3,},
Hu Hanzhi^{1, 2,},
Xie Mengyao^{1, 2},
Wang Zhe^{1, 2, ,},
Wu Chenggang^{1, 2,}

1.
State Key Lab of Processors (Institute of Computing Technology, Chinese Academy of Sciences), Beijing 100190
2.
University of Chinese Academy of Sciences, Beijing 100049
3.
Henan Institute of Advanced Technology, Zhengzhou University, Zhengzhou 450002

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Author Bio:
Lai Yuanming: born in 1991. PhD candidate. His main research interests include binary translation, computer systems security, and code obfuscation

Li Yalong: born in 2000. Master candidate. His main research interests include binary translation optimization and RISC-V architecture. (li2542369686@163.com)

Hu Hanzhi: born in 1999. Master candidate. His main research interests include binary translator optimization and compiler optimization. (huhanzhi22s@ict.ac.cn)

Xie Mengyao: born in 1992. PhD, associate professor, master supervisor. Her main research interests include computer system architecture and system security

Wang Zhe: born in 1990. PhD, associate professor, master supervisor. Member of CCF. His main research interests include computer systems security, operating systems, and computer architecture

Wu Chenggang: born in 1969. PhD, professor, PhD supervisor. Distinguished member of CCF. His main research interests include binary translation, compiler optimization, and computer systems security. (wucg@ict.ac.cn)
Received Date: February 28, 2025
Revised Date: April 08, 2025
Available Online: April 16, 2025

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Abstract

Abstract

RISC-V, renowned for its open-source nature and modular design, has achieved remarkable success in embedded systems and is progressively expanding into the high-performance computing (HPC) domain. While RISC-V hardware tailored for HPC, such as the Sophon SG2042 multi-core processors, has demonstrated performance comparable to x86/ARM counterparts, its underdeveloped software ecosystem remains a critical barrier to broader adoption. To address this challenge, we develop RVBT, a process-level dynamic binary translator for RISC-V, designed to bridge the software gap by efficiently porting the mature x86 ecosystem to RISC-V platforms, thereby accelerating RISC-V’s integration into HPC applications. Focusing on the pervasive use of SIMD instructions in HPC programs, we tackle the inefficiencies arising from fundamental differences in programming models between x86 SIMD and RISC-V vector (RVV) extensions. Specifically, x86 SIMD hardcodes data types within opcodes, whereas RVV dynamically configures vtype and mask registers, leading to redundant operations during direct translation. To overcome this, we propose three innovative optimizations to achieve: 1) Redundancy elimination via data type locality. By leveraging the locality of data types in adjacent SIMD operations, we statically analyze and remove redundant configurations of vtype (achieving 100% dynamic elimination rates for csrr and vsetvl, and 56.31% for vsetvli) and mask settings (74.66% elimination rate in floating-point benchmarks). 2) Hybrid translation with on-demand synchronization. We decouple scalar and vectorized floating-point operations, translating x86 SIMD scalar double-precision instructions to RISC-V’s floating-point extensions and reserving RVV for vectorized operations. Data synchronization between scalar and vector registers is optimized through def-use analysis, achieving a 67.35% dynamic synchronization reduction in floating-point benchmarks. Experimental results on SPEC CPU 2006 demonstrate significant improvements on the optimized RVBT, achieving 47.39% and 40.06% of native execution efficiency for integer and floating-point benchmarks, respectively, representing speedups of 1.21 times and 8.31 times over the unoptimized version. RVBT vastly outperforms QEMU (18.84% and 4.81% for integer and floating-point), with floating-point efficiency surpassing QEMU by 8.33 times, highlighting its potential for deployment in specific HPC scenarios. Crucially, these optimizations are architecture-agnostic: The methodology of exploiting data type locality, hybrid instruction translation, and adaptive synchronization apply equally to ARM SIMD (e.g., NEON) to RVV translation, offering a universal framework for cross-ISA binary compatibility. This work provides a pivotal technical foundation for breaking the software ecosystem deadlock and advancing RISC-V’s role in HPC.

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References (69)

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