Low-Power and High-Speed VLSI Architecture Design of 2-D DWT/IDWT

Lan Xuguang, Zheng Nanning, Xue Jianru, Wang Fei, and Liu Yuehu

Journal of Computer Research and Development > 2005 > 42(11): 1889-1895.

Lan Xuguang, Zheng Nanning, Xue Jianru, Wang Fei, and Liu Yuehu. Low-Power and High-Speed VLSI Architecture Design of 2-D DWT/IDWT[J]. Journal of Computer Research and Development, 2005, 42(11): 1889-1895.

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Low-Power and High-Speed VLSI Architecture Design of 2-D DWT/IDWT

Lan Xuguang, Zheng Nanning, Xue Jianru, Wang Fei, and Liu Yuehu

(Institute of Artificial Intelligence and Robotics, Xi'an Jiaotong University, Xi'an 710049)

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Published Date: November 14, 2005

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Abstract

Abstract

A low-power, high-speed and minimum-area architecture which performs two-dimension discrete wavelet transform (2-D DWT) of JPEG2000 is proposed by using a line-based and lifting scheme. The architecture consists of one row processor and one column processor. The row processor, which is time-multiplexed, computes in parallel with the column processor, and two pixels can be encoded in one clock cycle. The extensions at the boundaries are implemented by an embedded circuit, and the memory is minimized. The whole architecture, which is optimized in pipelined way to speed up and achieve higher hardware utilization, has been implemented in FPGA, and can be used as a compact and independent IP core for JPEG2000 VLSI implementation.
- 2D discrete wavelet transform,
- VLSI,
- JPEG2000,
- parallel architecture,
- lifting schemes,
- line-based

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