A VLSI Architecture for PMVFAST Block-Based Motion Estimation Algorithm

A flexible, efficient and low power architecture for PMVFAST, an enhancing block-based motion estimation algorithm, is proposed in this paper. The core of the a rchitecture is a motion estimation engine, which supports independent calculatio n of SAD and several searching patterns with different sizes and types. The engi ne includes three types of delay variable units, which support arbitrary delay i n particular ranges and enable different pattern searching. The engine reuses pr ocessing elements to construct a SAD engine and enables basic support of all BMA s. Besides, the engine can reduce power consumption by gating the unused element s and reusing resources. Experimental results verify the superiority of the prop osed architecture. Its computing efficiency is about 15 times higher than the we ll-known low power FS architecture including 16 PEs and its PSNR is similiar to the FS algorithm.