A Low Power Data Cache Design Based on Very Narrow-Width Value

Today, lowering power consumption has become one of the most critical design concerns. Most modern microprocessors employ on-chip caches to bridge the enormous speed disparities between the main memory and the central processing unit (CPU), but these caches consume a significant fraction of the total power. It becomes increasingly important to design power-efficient cache memories. The very narrow-width values (VNVs) that need only a few bits to store occupy a large portion of cache access and storage. Based on this observation, a low power very narrow-width value cache (VNVC) which exploits the prevalence of VNVs stored in the cache is proposed. In VNVC, the data array is divided into low-bit array and high-bit array. At the control of an additional flag bit, the higher bits of the data cells that store VNV are closed to save its dynamic and static power consumption. VNVC achieves low power consumption only by the modification of the data array without any extra assistant hardware, and does not impact cache performance. Thus it suits for most kinds of cache organization. Experiments on 12 Spec 2000 benchmarks show that on average 4-bit width VNVC can obtain the best improvement, providing 29.85% dynamic and 29.94% static power reduction.